With the continual miniaturization of the semiconductor power module, the process dimension for the packaging process of the semiconductor power module is constantly shrinking and the square flat pin-free packaging (a surface-mounted semiconductor packaging technique) of the power module emerges. The technique enables the circuit function at target size, which was only possible with multiple discrete packaged devices before. Furthermore, as far as the electric performance is concerned, it eliminates unnecessary resistors and inductors, thus enabling a device with higher power density than discrete devices with the same packaging size. The power modules packaged in this way are gaining more and more market shares thanks to their high reliability, small power loss, and low development cost.
For the power modules of the square flat pin-free packaging structure, since the heat loss of the power chips are much larger than that of the driving chip, if the same kind of heat dissipating means are used for both the driving chip and the power chips, the utilization of the packaging space would be hampered, and a local heat buildup may result, causing premature aging effect to some chips well within their service lives, thereby negatively impacting the reliability of the product, leading to a shortened service life or even malfunction.
In the inventive power module of the square flat pin-free packaging structure, metal supporting pillars are used to elevate the structural layer where the driving chip lead frame resides, the height of the structural layer where the power chips reside remains unchanged, and the power chip lead frames and the metal heat dissipating disks extend into the area below the driving chip lead frame, thereby increasing the area of the metal heat dissipating disks corresponding to the power chips, accelerating the heat dissipation of the power chips which have large thermal design power (TDP).
Meanwhile, since the copper lead frames and the metal heat dissipating disks corresponding to the power chips with large TDP expand in area, main heat dissipating paths for the power chips spread on a larger area, such that there is a more uniform temperature distribution on the packaged module, preventing the excessive local heat buildup on the module and improving the reliability of the product. Furthermore, Due to the optimization of the heights of various structural layers, there is a height difference between two ends of the metal electrode lead, which alleviates the gravity-induced collapse of the electrode lead, reducing the occurrence of short-circuits, the difficulty in processing and the manufacturing cost.